1. Field of the Invention
The present invention relates to a power-on detector which detects power-on in a semiconductor integrated circuit device or the like, and a power-on reset circuit which initializes a register or latch circuit upon power-on.
2. Description of the Related Art
A conventional power-on detector is constituted by series-connecting a resistor and a diode or diode-connected transistor, and connecting the connection node to the input terminal of an inverter. The power-on detector generates a power-on detection signal by utilizing the fact that an output from the inverter is inverted as the power supply voltage rises upon power-on.
FIG. 1 is a circuit diagram showing an arrangement example of such conventional power-on detector. The source of a p-channel MOS transistor 11 is connected to a power supply VDD, and the drain and gate are connected to one terminal of a resistor 12. The other terminal of the resistor 12 is connected to ground VSS. The connection node between the drain of the MOS transistor 11 and one terminal of the resistor 12 is connected to the input terminal of a CMOS inverter 15 comprised of a p-channel MOS transistor 13 and n-channel MOS transistor 14. A power-on detection signal PDS is output from the output terminal of the CMOS inverter 15.
In this arrangement, when the semiconductor integrated circuit device is powered on, the potential of the power supply VDD increases. When the potential of the power supply VDD reaches a circuit operable level, the potential at the connection node between the diode-connected MOS transistor 11 and resistor 12 becomes higher than the circuit threshold voltage of the CMOS inverter 15. As a result, the output voltage (power-on detection signal PDS) of the CMOS inverter 15 changes to low level (“L” level). The potential of the power supply VDD further increases. When the potential at the connection node between the MOS transistor 11 and the resistor 12 becomes lower than the circuit threshold voltage of the CMOS inverter 15, the output voltage of the CMOS inverter 15 is inverted to high level (“H” level), and power-on is detected.
The power-on detection level can be controlled by adjusting the resistance value of the resistor 12 or the channel length/channel width ratio (L/W) of each of the MOS transistors 11, 13, and 14.
A technique of detecting power-on by the output signal PDS from the CMOS inverter 15 via a noise-cut low-pass filter (LPF) has also been known. The use of the low-pass filter can enhance noise resistance.
In the above-mentioned arrangement, however, the power-on detection level varies upon a change in temperature condition or variations in manufacturing process. This may result in a defective chip. For example, an onboard semiconductor integrated circuit device must normally operate within a wide temperature range of −40° C. to +125° C. A great change in temperature condition changes the threshold voltages of the MOS transistors 11, 13, and 14. The level at which the power-on detection signal PDS is inverted greatly varies. The resistor 12 is generally a diffused resistor. The resistance value of the diffused resistor readily varies upon variations in manufacturing process. Such variations cannot be fully coped with by adjusting the resistance value of the resistor 12 or the channel length/channel width ratio of each of the MOS transistors 11, 13, and 14.
When a semiconductor integrated circuit device incorporates a low-voltage circuit which operates around 1 V, the influence of a change in temperature difference or variations in manufacturing becomes more prominent. It becomes difficult to detect power-on.
To solve this problem, a technique of detecting power-on by using a circuit with low temperature dependency, such as a band gap reference circuit is proposed (see, e.g., Jpn. Pat. Appln KOKAI Publication Nos. 2002-43917 and H10-207580). However, no prior art can sufficiently reduce temperature dependency because an output voltage from the band gap reference circuit and a voltage prepared by resistance-dividing a power supply voltage are compared, in other words, a voltage free from temperature dependency and a voltage with temperature dependency (though temperature dependency is relatively low) are compared. Such technique is not satisfactorily applied to an onboard semiconductor integrated circuit device which is used under strict conditions.
The same problem occurs when a power-on reset circuit for initializing a register or latch circuit in a semiconductor integrated circuit device upon power-on is constituted using the above-described power-on detector. Demands have arisen for a measure against this problem.